1. Technical Field
The present invention relates to a method and apparatus for data processing in general, and in particular to a method and apparatus for address translation within a cache memory. Still more particularly, the present invention relates to a method and apparatus for translating an effective address into a real address within a cache memory.
2. Description of the Prior Art
In a typical data processing system, an access to a system memory usually involves a computation of an effective address via a summation of two numbers. For a data access, the two numbers may be, for example, a base address of a data array and an offset from the base address of the data array to the required data. For an instruction fetch, the two numbers may be, for example, an address of a current instruction and a relative displacement to the current instruction.
By the same token, an access to a cache memory also involves a computation of an effective address by summing two numbers. The computed effective address is then translated to a real address for a true cache "hit" verification. Because the translation of an effective address to a real address may take several processor clock cycles, various cache related mechanisms such as a Segment Lookaside Buffer (SLB) and a Translation Lookaside Buffer (TLB) are utilized to speed up the translation process. To further improve the translation process, many cache designs employ a content-addressable memory (CAM) to store multiple pairs of effective address and real address. The CAM is searched by simultaneously comparing the computed effective address against all stored effective addresses. If a match occurs, the corresponding real address stored together with the matched effective address is read from the CAM for a true cache "hit" verification.
Referring now to the drawings and in particular to FIG. 1, there is depicted a block diagram of an adder for generating an effective address to access a CAM, according to the prior art. As shown, two n-bit numbers A and B are added by an n-bit adder 11 to produce an n-bit sum A+B. The n-bit sum A+B is then supplied to a CAM 12 for comparison. If a match occurs within a matching section 13 of CAM 12, a corresponding data entry, such as a real address, within an association section 14 of CAM 12 will be output as M.
One problem associated with the prior art configuration for producing an output M is that adder 11 requires a significant amount of processor clock-cycle time to produce a sum A+B, resulting in additional latency for a cache access. Consequently, it would be desirable to provide an improved method and apparatus for translating an effective address into a real address within a cache memory such that the latency associated with a cache access can be reduced.